Scleral coil voltages are filtered and amplified by ultra-low noise amplifiers (Analog Devices, AD8331) before digitization and demodulation. The AD8331 includes a single-ended pre-amplifier followed by a variable gain amplifier (VGA) and a selectable gain post-amplifier. A software command from a personal computer user interface sets VGA gain using a digital-to-analog converter (Texas Instruments, DAC7574). For the scleral coil design described above, the overall amplification is configured to provide ~100x gain of raw scleral coil signals. Bandpass filters are located at three stages throughout the amplification circuitry, with overall cutoff frequencies between 24 kHz and 1.5 MHz. After amplification, each coil’s amplified signal is digitized using a 12-bit, high-performance analog-to-digital converter (ADC, Texas Instruments, ADS5242). The FPGA then simultaneously samples up to 12 scleral coil signals at 25 Msamples/sec each and then demodulates them using a multiply accumulate (MAC) unit. This high sample rate improves noise performance via two variations on oversampling. First, the 25Msamples/S rate is about 4–8 times the Nyquist rate required for sampling the output of the 24kHz-1.5MHz bandpass preamplifiers. Oversampling by 22n = 4 times the Nyquist rate reduces ADC quantization noise and effectively adds n≈1 bit to the 12-bit ADC’s effective resolution, depending on the spectral content of the signal and the degree to which the noise is uncorrelated with the signal. [25 ],[26 ] The MAC unit multiplies each signal by three pseudo-sinusoids (with the same frequency and phase as the field) to extract each component of scleral coil angular position. To report X, Y, and Z coil signal components at a final rate of 1kSample/s, the FPGA performs a MAC operation over N=245, 498, and 763 cycles, respectively, of the scleral coil signal multiplied by the corresponding field coil driving signal. To the extent that noise at this stage in processing is uncorrelated with signals, this averaging would yield a √N≈16–28-fold reduction in noise amplitude relative to signal amplitude In addition to reduced noise, this approach also achieves much higher bandwidth relative to [14 (link)], which handled noise by passing analog-demodulated signals through a bank of 200Hz 8-pole Butterworth analog low-pass filters.. User interface software written in C and running on a PC acquires the demodulated signal at 1 kHz via a UM232H-B-NC serial-to-USB interface (Future Technology Devices International Limited).
The FPGA also provides digital pulse train driving signals for the magnetic fields. The pulsatile driving signals operate at 20% duty cycle to reduce high-current load on the MOSFET circuitry while generating strong enough fields to obtain a scleral coil signal well above the system’s noise floor. This duty cycle is software programmable. Adjusting it can increase field intensity, increasing signal strength for smaller scleral coils.
The FPGA also provides digital pulse train driving signals for the magnetic fields. The pulsatile driving signals operate at 20% duty cycle to reduce high-current load on the MOSFET circuitry while generating strong enough fields to obtain a scleral coil signal well above the system’s noise floor. This duty cycle is software programmable. Adjusting it can increase field intensity, increasing signal strength for smaller scleral coils.
